The lightly doped drain (LDD) metal oxide semiconductor (MOS) field effect transistor (FET), or LDD MOSFET, is a transistor that has a drain region and a source region, each with a shallow lightly doped region adjacent a channel region, and a deeper, heavily doped region adjacent the shallow lightly doped region. The LDD MOSFET was developed by the integrated circuit industry for several reasons. The main reason for developing the LDD MOSFET was for use in reducing a known and understood hot carrier injection phenomenon. Hot carrier injection can degrade device performance and device lifetime and LDD formations are successful in reducing hot carrier injection effects.
To improve the performance of the LDD MOSFET over time, transistor material layer thicknesses and LDD MOSFET cell surface areas were reduced. Because of these advances and reductions, known phenomenon such as threshold voltage instability caused by boron penetration, doping outdiffusion, short channel effects, leakage currents, increased capacitance, and reduced isolation caused integrated circuit designers to search for new methods of making new LDD transistors more reliable.
Integrated circuit designers developed an elevated source and drain MOSFET to overcome some of the problems discussed above. The elevated source and drain MOSFET used source and drain regions physically raised off of the substrate surface to reduce short channel effects and doping outdiffusion. The elevated source and drain MOSFET has the disadvantage of having a high probability that a salicide or silicide layer could electrically short a source or drain to the substrate via a known spiking phenomenon. The spiking phenomenon is usually related to faceting in epitaxial growths along material boundaries. Faceting is a phenomenon that causes non-uniform or retarded growth epitaxial regions along epitaxial-to-dielectric boundaries. The electrical shorting caused by faceting or spiking renders the electrically shorted device inoperable. The elevated source and drain MOSFET also has the disadvantage of producing source and drain regions that may not have a constant junction depth. This variation in junction depth can effect device performance, capacitance, isolation, and other essential device characteristics and parameters.
While the LDD and elevated source and drain MOSFETs were still in need of improvements, bipolar and complementary metal oxide semiconductor (CMOS) transistors were being merged into a new technology commonly referred to as BiCMOS. BiCMOS technology added new problems and considerations to the course of research in MOSFET technology. BiCMOS technology, for most processes, usually results in added processing steps and therefore added process complexity. Conventional BiCMOS technology can also result in devices that further hinder device size reduction and device performance in both the bipolar regime and the CMOS regime. Currently, a process or a device that eliminates the disadvantages of the LDD and elevated source and drain MOSFETs does not exist.